write to segment (multiple locations) of memory

You just described a "many port" RAM which doesn't exist as dedicated hardware in an FPGA (highest I've ever heard of is 6/8 port memory but that's in the ASIC space).

You can mimic this by using a bunch of little memories but by the sounds of how many locations you want to access at once that might not be practical for your design. You could use the memory in a wider mode so that multiple byte lanes get accessed concurrently. For example for a 128x8 you could use a 256x32 M9K in true dual port mode and write 8 byte lanes all in one shot. Then duplicate the memory to span the depth you want...... again this is going to become expensive.

Do you need the writes to complete in a single cycle? A simple DMA type of engine could be used to write the same value sweeping from a start address. You won't be able to access all the addresses in one clock cycle but this would be way cheaper than trying to implement a many port on-chip memory.

The alternative is to build this out of registers to mimic having many ports. You would treat each 8-bit register as a memory location and so your write enable would be just the clock enable of the flipflop. You would need some deep muxing logic to read a value out of your memory since it would be an 8-bit mux with 128 inputs per bit so you would have to pipeline that to get some decent speed out of it.