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Altera_Forum
Honored Contributor
14 years agowrite master and waitrequest
hi, i have a custom memory mapped write master. I want initialize a piece of the memory with all zeros, and after that, write a sub-part of these piece of memory with data coming from a fifo. ...
Altera_Forum
Honored Contributor
14 years agoYou don't need an asynchronous mux. The write data vector needs to be sent at the same time than the write control signal and the address. If all of them are registered from the same place it will work. Then you only continue writing to other addresses when you read a waitrequest signal at 0.