wr3_addr and wr4_addr

could someone explain me the following verilog example.

I don't understand why the wr4_addr is 22'h280000 instead 22'h200000+320*256+1, i think that it is a choice of the programmer or has someone other reasons?

thanks

// FIFO Write Side 3

.WR3_DATA({1'b0, sCCD2_G[4:0], sCCD2_B[9:0]}),

.WR3(sCCD2_DVAL),

.wr3_addr(22'h200000),

.WR3_MAX_ADDR(22'h200000+320*256),

.WR3_LENGTH(9'h100),

.WR3_LOAD(!DLY_RST_0),

.WR3_CLK(CCD2_PIXCLK),

.WR3_FULL(Full[2]),

// FIFO Write Side 4

.WR4_DATA( {1'b0, sCCD2_G[9:5], sCCD2_R[9:0]}),

.WR4(sCCD2_DVAL),

.wr4_addr(22'h280000),

.WR4_MAX_ADDR(22'h280000+320*256),

.WR4_LENGTH(9'h100),

.WR4_LOAD(!DLY_RST_0),

.WR4_CLK(CCD2_PIXCLK),

.WR4_FULL(Full[3]),