wr_clk1x_rd_clk2x

hi all !

I have generated ram macro from megawizard(attachment file), then i created a wrapper for it with write by clk1x clock and read by clk2x clock.

when read ram, i want data to appear early 1 clk1x clock (when read by clk1x clock, data appear after 2 clk1x clock)

i intend use it for cyclone iv device, please give me advise about this, how about timing of read/write ram.

clk1x = 77.76Mhz, clk2x = 155.52Mhz, phase is 0 degree as attachment picture.

Thanks all advises !

module wr1x_rd2x

(

clk1x,

wren,

wraddress,

data,

clk2x,

rden,

rdaddress,

q

);

input clk1x;

input wren;

input [9:0] wraddress;

input [7:0] data;

input clk2x;

input rden;

input [9:0] rdaddress;

output [7:0] q;

wire rden2x;

wire tmp;

wire nxt_tmp;

fflopx# (1,1) cr_tmp(clk2x,rst_,nxt_tmp,tmp);

assign nxt_tmp = rden ? (~tmp) : 1'b1;

assign rden2x = rden & tmp;

altsyncram112x_2clk# (1024,8) altsyncram112x_2clk

(

.wrclock (clk1x),

.wren (wren),

.wraddress (wraddress),

.data (data),

.rdclock (clk2x),

.rden (rden2x),

.rdaddress (rdaddress),

.q (q)

);

endmodule