Workaround for wrongly assigned DQS pin for DDR SDRAM controller in Cyclone IV FPGAs

Your second workaround is very inventive and, IMHO, will work 100%.

In Cyclone IV the DQS strobes are not used to strobe in the read data coming from the DDR device. In stead a PLL-generated clcok is used to capture these read data.

Writing some selected values for a memory test is a bit simple, if you truly want to test your memory you need to generate quite complicated patterns to exercise the silicon at its fullest. But to verify whether Altera's IP is functioning it will suffice.