Honored Contributor
Honored Contributorquantized -
Have you looked at everything that is affected when a second card is plugged in? Before an FPGA is configured all of its programmable I/O are tri-stated and weakly pulled high by internal pullups. Are there any common signals that could be affected by this? How about the programming pins? Anything shared between cards or does each card configure itself? What you described does not make any sense if the 10Mhz clock is not affected by the second card and there are no other interactions that could cause the problem. There is obviously a cause and effect here. You just have to figure out what it is. What all can cause a PLL to lose lock? Loss or corruption of the input clock, reset (explicit or due to loss of configuration such as due to trip of POR circuit), power supply noise, etc. Identify all of the possibilities and then look at all the possible ways the second card could be a factor. Interesting problem!
