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I guess a high frequency difference between in and out could lead to a limited locking range.
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Hi Cris, the Cyclone III PLL (and most PLLs for that matter) don't have direct constraint on the difference between the input and output frequency.
There's a limited range for the VCO, but even at its slowest (600mhz) it runs faster than the clock network is able to.
Basically the PFD nudges the VCO to a near-gigahertz multiple of the input clock, and then the output counters divide that down. The output counters have no effect on the VCO, so the output frequency does not affect the PLL's ability to lock (the VCO parameters do, of course affect it).
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In the Quartus compilation report you should find the min and max frequency values.
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Yeah, I checked those. Claimed a lock range of 5.60-12.04mhz. I'm inside by 20%.
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In any case you can try to cascade two PLLs if you have spare resources: the first one would raise clock frequency from 10MHz to a conveniently high intermediate frequency that the PLL can easily manage, say 100MHz; then you tune the second PLL to the required frequency.
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Yeah, I tried that, the first PLL loses lock.
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