Honored Contributor
Honored Contributor(posting this here in case others run into the same problem -- for every question I ask on this forum it seems I solve ten by reading the archives... it's an amazing resource to have, especially for somebody who had "brand X" drilled into their head in grad school)
Unfortunately I can't say I've solved the problem, and it's still deeply disconcerting. However I did manage to establish that the 10mhz base clock is involved in the problem. The PCB has one of the GCLK input pins tied back to an output pin, so I hooked up that output pin to the 60mhz-ish internal oscillator (altint_osc), brought it back onto the chip (why oh why do you make us send the signal off-chip?), sent it through a PLL with an obscenely low bandwidth (Ipump=0, Rfilt=30, Cfilt=3). It's rock solid. Even coming from an internal oscillator. Periodically measure the actual frequency from off-chip and reconfigure the PLL to bump the multiplier up/down as needed in response to temperature changes although so far that has not been necessary (and one could even argue that you want the clock to slow down when the room warms up). So it's fixed for now, but I'm still deeply disturbed by the fact that the PLL somehow couldn't hold a lock on the 10mhz clock. At such low speeds it ought to be possible to trust what you see on even a low-end 100msps oscilloscope, no? Because the waveform was the nice clean shape you'd expect. Is the fact that this input is so slow a source of trouble? The internal oscillator is ~6x faster. Oh well. It's fixed for now, but if anybody has further insights I'm still interested. I'd like to be able to go back to the quartz clock in the future if necessary. Unfortunately respinning the PCB to give each FPGA its own private oscillator isn't really an option.
