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Is the base clock wave somehow affected by the insertion of more than one board?
I mean, do you observe any change in duty cycle, level or wave shape compared to the case when you have one single board?
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Definitely not; that's what I meant when I wrote the following, although perhaps I wasn't making it clear:
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I've probed the shared 10mhz clock, ... on a scope, and nothing budges by more than 5mV, which is less than 1%. In particular the clock waveform is the nice smooth curve you'd expect.
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The presence of the second card definitely doesn't affect the clock waveform by more than 1%. That trace is driven by a pretty powerful buffer/line-driver IC (not directly by the clock can).
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Does the base clock travels a long path in the backplane?
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Yes. Total trace length on the backplane is around 180mm, plus eight card-edge connectors and another 30mm or so on each plugged-in card. That's a lot, but keep in mind it's only a 10mhz clock.
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Do you use any termination on the trace?
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No, mainly because it's such a slow clock. Probing doesn't show any ringing at all.
Also, nothing is actually synchronous to that 10mhz clock; it serves only as a source for the FPGA PLLs to produce the high-speed DDR clocks. Communication with the "outside world" is entirely via JTAG at low speeds (~500kbit/sec, synchronous to TCK, which is terminated on each board).
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Another guess: is possible that the big bulk capacitance is actually the reason of the problem? The added capacitance could slow down the power supply risetime and prevent correct resetting of the PLL circuitry.
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Hrm, I don't think so; the problem occurs even if I power up the system first (i.e. charge up all those huge caps; the 1200uFs are on the backplane) then plug in the cards after power-up.
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