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The F2S interfaces expose a 4GB address space so if your DMA is limitted in it's addressing capabilities you might need to put that address span bridge between it and the HPS. The DMA and SGDMA in Qsys only support up to 4GB but the mSGDMA up on
alterawiki.com supports up to 64-bit addressing if you enable the enhanced descriptors. So if you used the mSGDMA you wouldn't need the address span bridge.
Regardless of the DMA addressing capabilities you might want to expose only a subset of the full 4GB SDRAM range so that the addressing logic in the DMA is not as wide. That typically drops the Fmax of the design when you try to master lots of memory so you might want to limit the address span using the address span bridge. For example lets say you only want to make addresses 0x1000_0000 to 0x100F_FFFF (1MB window) available you could setup the address span bridge to expose a 1MB range and have it hardcoded to start at 0x1000_0000.
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I see! It makes sense.
I guess the same goes for the FPGA->SDRAM bridge with Altera Qsys DMA.
Just to make sure.
1. I've set the F2S SDRAM Bridge data to 64 bits WIDTH and write only, avalon-mm
2. I've added a SPAN EXTENDER, then i set the DATA PATH WIDTH to 64 bits and the ADDRESS WIDTH of the master to 32 bits (4 giga) and a default subwindow of 512kb
3. I've added an ALTERA DMA Controller and the WIDTH of the DMA LENGTH REGISTER is set to 32 bits
4. I've connected the DMA write master to the windowed slave on the SPAN EXTENDER
5. I've connected the expanded master to F2H_DATA
That's it? Now the Device Driver on HPS must set the right registers on the DMA Control port slave.
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