With the Cyclone V SoC, how can I use the FPGA fabric to access the HPS DMA?

You hit the nail on the head, Qsys will take care of any adaptation between the soft DMA logic and the interface into the HPS, that's why I use Qsys for integration because then I just worry about the IP being compliant to the interface spec and the tools will take care of gluing the IP together for me.

Unfortunately the design isn't very far along so it would be quicker to integrate it yourself. You would connect the lightweight H2F bridge to the slave port of the DMA so that the Cortex-A9 can control the DMA then connect the DMA masters to the HPS SDRAM ports. I said "ports" because you could have one port dedicated to reads and the other dedicated to writes and perform both reads and writes simulataneously and the HPS SDRAM controller will interleave them out to memory for you. If you use an existing DMA then I would select Avalon-MM ports for the SDRAM interface into the FPGA since the DMAs in Qsys are already Avalon-MM based (you can mix Avalon and AXI but that's just a waste of logic resources in this case).