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Altera_Forum
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11 years ago

With the Cyclone V SoC, how can I use the FPGA fabric to access the HPS DMA?

Hello everyone, I want to make something that records values that are in my FPGA. I thought of using the Cyclone V SoC DMA, I do have the Altera SoC kit. With the Cyclone V SoC, how can I ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Actually I have a design planned to do exactly this but unfortunately it's not ready yet. You don't necessarily need to fence off a region of memory for the FPGA to access, you could dynamically allocate some space and pass the location to the FPGA logic to access later.

I think if you look at the golden hardware reference design there is a connection between some FPGA logic and the HPS SDRAM that you can take a look at. If I remember correctly there is a JTAG-to-Avalon memory mapped bridge connected which lets you peak and poke memory using system console. You'll want something more self contained but it would be a good starting point to look at to see how to configure the memory controller to give the FPGA access to it.

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Yup I saw this ref design, however it uses the F2H and H2F bridges and not the F2SDRAM, Can I just instiantiate a DMA IP in QSys and connect to the F2SDRAM bridge? QSys magically takes care of everything for me?

Could you share with me this "beta design" you have? My e-mail is wcprado { AT } hotmail { dot } com