Forum Discussion
Altera_Forum
Honored Contributor
11 years agoThere are up to 6 FPGA-to-SDRAM ports that you can push that data directly into the HPS SDRAM controller from the FPGA. If it was me I would just use those to push the data in directly and interrupt the processor after the data has been written to memory. Alternatively you could push the data through the F2H bridge into the ACP mapper so that the processor has a cache coherent view of the data automatically (depends on how much data you are sending over).