New ContributorHello,
I'm using an Arria V FPGA with a native PHY configured to Rx mode only.
The PHY receives serial data in an 8b/10b format.
My question is regarding the "Word Aligner".
I understand that it supports 3 types of operation:
If it's configured to "bit slip" will the Rx block auto align the word?
Or will I have to write additional logic to take care of alignment?
Regular ContributorHi skon,
As I understand it, you have some inquiries related to AV word aligner configured in bitslip mode. For your information, in bitslip mode, it will not perform auto alignment. You would need to create your own logic to control it. The high level idea of the control logic would be to perform one bit slip and then check if the RX parallel output consists of your expected word alignment pattern. If not, then repeat the bit slip insertion and checking until you see the word alignment pattern sent.
Please let me know if there is any concern. Thank you.
Chee Pin
Chee Pin
Regular ContributorHi skon,
As for state machine mode, it will perform auto alignment after XCVR coming out from reset. It will look for pre-defined word alignment pattern configured in Native PHY. For the Manual mode, it is almost similar to state machine mode but just that user will need to manually trigger to start the alignment process.
Please let me know if there is any concern. Thank you.
Chee Pin
Chee Pin
