New MemberI was hoping to use LVDS serdes IP to implement acquisition system of 12 -bit ADC data using 2-wire LVDS:
However, this is not possible if only serialization factors of 4 and 8 are supported.
Is there a workaround or will this be supported in the future?
Super ContributorHi,
Agilex 3 and 5 SERDES are apparently limited to 4 and 8 deserialization factor. I'd assume for the time being that the restriction is in silicon and can't be overcome by software. See e.g. this previous discussion
Deserializers in Agilex 3 series | Altera Community - 324280
For x12 deserializer, I see an acceptable solution by using x4 deserializer, external 3x4 bit shift register and external PLL with FCLKx3 slow clock. Implementing e.g. x10 deserializer for popular 8b10b encoded links is more complicated, particularly when looking at synchronization logic. I'd appreciate an Altera reference design for 8b10b receiver with Agilex 3/5.
Regards Frank
