I made today some tests and found strange PLL behavior it outputs strange frequency in place of 16Mhz I get 22,7Khz frequency I set PLL to ratio 1/1 so it need to be 16Mhz, I tested it by making such test code where i created 2 clocks one direct 16Mhz clock input I routed to Global clock line and other was PLL clock and for testing I created logic 6bit(/128) frequency divider.
and as I have only 1Msps oscilloscope I saw that output of non PLL clock logic was 128Khz and it is correct, value for 16Mhz clock, but PLL clock I measured directly and it was 22,7Khz :(
Why PLL don't work correctly ??
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Entity Declaration
ENTITY Cyclone_III_pin_test IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
A : Out STD_LOGIC_vector(7 downto 0);
Clk : IN STD_LOGIC
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END Cyclone_III_pin_test;
Architecture Cyclone_test of Cyclone_III_pin_test is
signal CLK_1ms,B,B2,C,D: std_Logic;
signal Q,Q2 : STD_logic_vector (5 downto 0);
component C3PLL_test
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;
component clk_route
PORT
(
inclk : IN STD_LOGIC ;
outclk : OUT STD_LOGIC
);
end component;
begin
clk_16M : clk_route
Port map( inclk=>clk,outclk=>C);
CLock_PLL : C3PLL_test
Port map( inclk0=>clk,c0=>CLK_1ms);
--CLK_1ms<= CLK;
A(3) <= CLK_1ms;
A(2) <= CLK;
A(1) <= C;
A(0) <= CLK_1ms;
A(4)<= D;
process(clk_1ms)
begin
--if clk_1ms ='1' then
if rising_edge(clk_1ms) then
Q<=Q+1;
if Q ="000000" then
if B='1' then
A(7 downto 5)<= "111";
B<='0';
else A(7 downto 5)<= "000"; B<='1';
end if;
end if;
end if;
end process;
process(c)
begin
--if clk_1ms ='1' then
if rising_edge(c) then
Q2<=Q2+1;
if Q2 ="000000" then
if B2='1' then
D<= '1';
B2<='0';
else D<='0'; B2<='1';
end if;
end if;
end if;
end process;
end Cyclone_test;
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