Wierd Fifo RdReq problem

It sounds like the scaler block is doing something unexpected, not the FIFO. Now, the fact that it occurs in the simulink simulation makes me guess this is the way it is supposed to work. Are you able to do an RTL simulation(easier than SignalTap in that you can quickly and easily access all the nodes.) But the fact that simulation agrees with hardware usually means it's working as it's supposed to, this just may not be as expected.

I don't know anything about the scaler, but you might want to try simulating it by itself and just see what happens "differently" when it switches mode. My hunch is you'll find something(if it worked the same way, it wouldn't make sense that this is what initiates the change.) One other thing is that you probably only have one SignalTap clock, which means it is either related to the write clock or the read clock, but not both. So maybe you're missing an extra pulse in the other clock domain, or something like that. Maybe two writes occur when the scaler switches, which looks like it's missing a read in the read domain. But again, it really sounds like the FIFO is not the problem.