why the waitrequest signal is always 0

Actually I don't recommend that. Masters should issue read or write transactions regardless of the state of the waitrequest signal. From the master perspective, waitrequest just informs the master that the read/write transaction must be prolonged. The Qsys fabric has an undefined waitrequest behavior when the master is not issuing a read or write transaction so if your master is waiting for waitrequest to be low before issuing a transaction you might deadlock that master since it could wait indefentely.

The memory controller uses an active low waitrequest because it uses it's internal ready signal (so when it's not ready waitrequest should be issued back to the fabric). So when the slave port is ready to handle data you should see the SDRAM slave port waitrequest_n (should be called avl_ready_x, where x is the port number) set to 1. If you see it set to 0 that means either it has buffered up so many transactions that it needs to backpressure or it's command FIFO is full and it's still calibrating.