Forum Discussion
Altera_Forum
Honored Contributor
16 years ago --- Quote Start --- It could be timing failures. By routing a signal differently in the 2nd compile, the re-fit could cause previously failed timing paths to pass. This usually occurs in designs that are not fully syncronous. --- Quote End --- Hi, it is not only a different routing. By routing the signals to pins your are changing the synthesis itself, because this signals could not removed ( if possible) anymore. Did you have timing violations in your design ( setup or hold ) ? Kind regards GPK