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I've created digital designs for 5+ years. I have never used Qsys. I've written HDL modules, manually wired them, did timing analysis and eventually synthesize them. I never found the need to use Qsys.
Am I missing out on any benefits?
Why should I use Qsys?
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Basically it is meant to have several ips generated (as well as clock, reset generation) under one roof and wired together instead of module by module ip generation by the wizard. It also adds addressing map for memory mapped systems. All wiring between such modules are invisible unless you export them.
So in principle it is meant to phase out wizard for a complete subsystem and all such changes are forced on us...
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