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I have couple of silly questions regarding the interfacing...
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These questions are related to how a PCIe system is initialized. In PCIe the root-complex is responsible for setting up all the end-points. The "default" for a standard PC is that the BIOS sets up the PCIe memory windows at boot time. This fact causes the problems you are seeing. Here's several use-cases for you;
1. Power-on and manual FPGA download
Power-on your PC, and hit ESC (or whatever) to pause on the BIOS screen. Download your Stratix V kit PCIe end-point design. Exit the BIOS and allow your PC to continue booting.
When you exit the BIOS you are performing a warm-reboot, where the BIOS rescans the PCIe bus, finds your device, and configures it.
2. Power-on and auto FPGA download (configuration from on-board Flash)
This is similar to (1), except that the FPGA must configure within 100ms to ensure it is alive when the PC BIOS enumerates the PCIe bus.
3. Manual FPGA configuration after the PC has booted.
In this case, if you reconfigure the FPGA, the PCIe registers come up at their reset values, not with the values the PC "saw" when you powered-on the machine. You can "cheat" and manually reprogram the values that were previously in the PCIe end-point registers (if you wrote down their values), or you can force the PC to re-enumerate the PCIe bus (which is fairly easy under Linux).
If you read the PCIe specification, this should be in there somewhere.
Cheers,
Dave
Honored Contributor
