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Altera_Forum's avatar
Altera_Forum
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13 years ago

Why Quartus cannot recognise my state machine

Hi all,

We have implemented a state machine in a Stratix V project however we cannot find it in either state machine viewer or compilation report. Could anyone give some hints that does Quartus require some special format to recognise the state machine or we missed something? We have compared our state machine with others (automatically generated by Quartus) that can be recognised and we cannot see any format difference...

Thanks

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    You will see the states that way since Quartus will see the state machine and encode the states. Looks like Quartus re-encoded your states as one-hot and this happens to be Quartus's default.

    /Boris

    --- Quote End ---

    This is common. If you use Enums the synthesis tools may reencode the states. It is not just Quartus, Synopsys DC will do the same thing, but will use a binary encoding optimized to reduce the logic or perhaps the transitions.

    Now Quartus uses binary encoding as it is nicer for the FPGA structure, that gives you lots of flops and a little logic for each flop. A binary encoded FSM needs less flops but then requires much more complex combinatorial encoding. You can tell quartus to force a different encoding though, but the default is one hot.