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Altera_Forum
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14 years ago

Why Quartus cannot recognise my state machine

Hi all, We have implemented a state machine in a Stratix V project however we cannot find it in either state machine viewer or compilation report. Could anyone give some hints that does Quartus...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Dear skid,

first of all, i'm pretty bad at (system)verilog.

But nevertheless i've wrapped a module around your code as I understand it.

Because my module has only "dangling" ports as Quartus reports, it is synthesized away.

It's hard for me to predict what Quartus will do, if Ican't analyze it's output.

Best regards,

jb123