Why Quartus cannot recognise my state machine

Thanks for all the reply. Please see the code of the state machine. It is written by systemverilog so we use structure to define variables. Any suggestion would be highly appreciated

typedef struct packed {
    logic                 writedata;
    logic                  address;
    logic                       read;
    logic                       write;
} cpld_output_t;
localparam cpld_output_t cpld_default_output = '{
    default                     : 'x,
    read                        : 1'b0,
    write                       : 1'b0
};
typedef struct packed {
    logic                 readdata;
    logic                       readdatavalid;
    logic                       waitrequest;
} fabric_output_t;
localparam fabric_output_t fabric_default_output = '{
    default                     : 'x,
    readdatavalid               : 1'b0,
    waitrequest                 : 1'b1
};
typedef enum logic  {
    NO_OWNER                    = 2'b01,
    MM_OWNS                     = 2'b10,
    RAW_OWNS                    = 2'b11
} cpld_owner_e;
typedef enum {
    IDLE,
    RAW_WRITE,
    RAW_READ
} flash_mm_access_e;
typedef struct packed {
    logic                 mm_address_high;        // 12 bits
    cpld_owner_e                owner;                  // 2 bits
    flash_mm_access_e           status;                 // 3 bits
    cpld_output_t               cpld;                   // 22 bits
    fabric_output_t             cpld_raw;               // 18 bits
    logic     mm_burstcount;          // normally 8 bits
} state_t;                                              
state_t state, next_state;
localparam state_t default_state = '{
    mm_address_high             : 'x,
    owner                       : NO_OWNER,
    status                      : IDLE,
    cpld                        : cpld_default_output,
    cpld_raw                    : fabric_default_output,
    mm_burstcount               : 'x};
always_comb begin
        // default assignments
        next_state                  = state;
        next_state.cpld_raw         = fabric_default_output;
        case (state.status)
            IDLE: begin
                if (cpld_raw_read) begin
                    next_state.status               = RAW_READ;
                    next_state.owner                = RAW_OWNS;
                    next_state.cpld_raw.waitrequest = 0;
                    next_state.cpld.address         = cpld_raw_address;       
                    next_state.cpld.write           = 0;
                    next_state.cpld.read            = cpld_raw_read;
                end else if (cpld_raw_write) begin
                    next_state.status               = RAW_WRITE;
                    next_state.owner                = RAW_OWNS;
                    next_state.cpld_raw.waitrequest = 0;
                    next_state.cpld.address         = cpld_raw_address;       
                    next_state.cpld.writedata       = cpld_raw_writedata;
                    next_state.cpld.write           = cpld_raw_write;
                    next_state.cpld.read            = 0;
                end 
            end
            RAW_WRITE: begin
                next_state.cpld_raw.waitrequest     = 1;
                if (!cpld_waitrequest) begin
                    next_state.cpld.write           = 0;
                    next_state.status               = IDLE;
                    next_state.owner                = NO_OWNER;
                end
            end
            RAW_READ: begin
                next_state.cpld_raw.waitrequest     = 1;
                if (!cpld_waitrequest) begin
                    next_state.cpld.read            = 0;
                end
                if (cpld_readdatavalid) begin
                    next_state.cpld.read            = 0;
                    next_state.cpld_raw.readdatavalid = 1;
                    next_state.cpld_raw.readdata    = cpld_readdata;
                    next_state.status               = IDLE;
                    next_state.owner                = NO_OWNER;
                end
            end
                
           default: begin
                next_state = default_state; 
            end
        endcase
end
always @(posedge clk or negedge reset_n) begin
    if (~reset_n)
        state                   <= default_state;
    else
        state                    <= next_state;
end