Why Quartus cannot recognise my state machine

Look in the Quartus Language Templates, that will show if you edit a text-file in the Quartus-editor.

Go to [Verilog HDL|VHDL]/Full Designs/State Machines.

There you'll find aproppriate code.

We usually use the Moore State Machine Construct, with the exception that we clock the output states too.

We never had any problems with that, but we never compiled designs for Stratix V either.

Apart from that, ashihkaps is right:

If you don't post your code you're lost.