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allen18's avatar
allen18
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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why must I need to generate two jesd204b ip core when I use two ADC?

If the device clk and sysref of the two ADCs from a same clock chip, and I configure L M F ＝ 2 8 8 for each ADC, I need to instantiate two ip cores and configure L M F＝ 2 8 8. Why cannot I instantiate one ip core and configure L M F ＝ 4 16 8 ？

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Other Ips
  • ZH_Intel's avatar
    ZH_Intel
    2 years ago

    Hi Allen,

    Apologize for the delayed response.

    Regarding to your question, If both share the same IP, there is no mechanism to check and ensure that the data are aligned. The data transmitted by the two ADCs will not be synchronized, high likely will arrive at different times. With multiple JESD IP, even if data can arrives at different time, there is a mechanism to ensure the RX IP data can align and then achieve synchronization behaviour.

    The below concept is for JESD204C, which is applicable to JESD204B too.

    Screenshot

    Hope this answers your question.

    Best Regards,

    ZulsyafiqH_Intel

3 Replies

  • ZH_Intel's avatar
    ZH_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Allen,

    Thank you for reaching out.

    Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.

    I shall come back to you with findings.

    Thank you for your patience.

    Best Regards,

    ZulsyafiqH_Intel


  • ZH_Intel's avatar
    ZH_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Allen,

    Apologize for the delayed response.

    Regarding to your question, If both share the same IP, there is no mechanism to check and ensure that the data are aligned. The data transmitted by the two ADCs will not be synchronized, high likely will arrive at different times. With multiple JESD IP, even if data can arrives at different time, there is a mechanism to ensure the RX IP data can align and then achieve synchronization behaviour.

    The below concept is for JESD204C, which is applicable to JESD204B too.

    Screenshot

    Hope this answers your question.

    Best Regards,

    ZulsyafiqH_Intel

  • ZH_Intel's avatar
    ZH_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi Allen,


    Thank you for your respond.

    I’m glad that your question has been addressed, with that, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


    Thank you.

    Best Regards,

    ZulsyafiqH_Intel


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