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Altera_Forum
Honored Contributor
Honored ContributorWhy is the use of different PLL feedback modes in Altera devices?
The documentation states that the Altera PLLs have 6 different clock feedback modes. These are: 1. Direct mode 2. Normal mode 3. Source-Synchronous mode 4. External Feedback mode 5. Ze...
Altera_ForumHonored Contributor
Honored Contributorif I am connecting a audio DAC that needs MCLK (master clock) and takes I2S signals SCLK, Data and LRCK (same frequency as audio sample rate, used to select left/right channels), and I intend to generate MCLK and other clock signals from a PLL inside the FPGA, which of these shall I need to use?
