Forum Discussion
Altera_Forum
Honored Contributor
14 years agoRysc has once posted VHDL code in another forum thread which implements content addressable memory with block rams in Stratix devices. You can find this thread here:
http://www.alteraforum.com/forum/showthread.php?t=2153&gsa_pos=6&wt.oss_r=1&wt.oss="content%20addressable%20memory" (http://www.alteraforum.com/forum/showthread.php?t=2153&gsa_pos=6&wt.oss_r=1&wt.oss="content%20addressable%20memory")