Why does quartus think my signal is a clock?

Looking at this further, I'd also synchronize the 3rd process using clk and reset signals.

You're executing loops and updating internal signals and variables as a result, but there is no explicit state machine. I wonder why. I don't write code, nor do I teach students to write it this way, as it is much more evident what is going on if the state machine is explicitly defined in its own process (states as enumerated values of a state variable, and a process with a Case construct to execute next state transitions based on present state and any inputs that affect next state decisions). Then your data path operations would be in one or more separate processes. Any non-clocked, asynchronous data path operations would be in their own processes, with input signals and not the clk in their sensitivity list.

Just a thought.

regds,

jim