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Altera_Forum
Honored Contributor
Honored ContributorWhy does quartus think my signal is a clock?
Here is the code snipped begin
write_register <= '1' when ((chipselect = '1') and (write = '1') and (byteenable = "1111") ) else '0';
process (clk,reset_n)
begin -- process
if reset_n...
Altera_ForumHonored Contributor
Honored Contributorclearly enable is not a clock in the usual meaning of edge triggering signal. I assume quartus is not saying it is clock but timequest.
The signal out_register(i)(j) will become all latches enabled on your enable and I believe timequest just regards it as clock.
