Why does quartus think my signal is a clock?

I changed the code to this but the problem persists

process (clk,reset_n)
  begin  -- process    
	if reset_n = '0' then
	out_settings <= x"FEDCBA9876543210";
    elsif rising_edge(clk) then 
	 enable <= '0';
      if (write_register = '1') then
        case address is
          when '0' =>
            out_settings(31 downto 0) <= writedata;
          when '1' =>
            out_settings(63 downto 32) <= writedata;
				enable <= '1';
				  when others =>
				    enable <= '0';
        end case;
      end if;
    end if;
  end process;
  process (enable,out_settings) is
  begin 
	 if enable = '1' then
    for i in 0 to (N_CHANNELS_ANA - 1) loop
        for j in 0 to 3 loop
          out_register(i)(j) <= out_settings(i*4 + j);
        end loop;
    end loop;
	 end if;
  end process;
  process (ana_bits_in, out_register)
    variable index : integer range 0 to (N_CHANNELS_ANA - 1);
  begin
    for i in 0 to (N_CHANNELS_ANA - 1) loop
	 index         := conv_integer(out_register (i)(3 downto 0));
      ana_bits_out(i) <=  ana_bits_in(index);
    end loop;
  end process;