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Altera_Forum
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12 years ago

Why does quartus think my signal is a clock?

Here is the code snipped begin write_register <= '1' when ((chipselect = '1') and (write = '1') and (byteenable = "1111") ) else '0'; process (clk,reset_n) begin -- process if reset_n...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

In the second process you write:

out_register <= out_register

out_register behaves like a latch, so you need a latch enable. May be Quartus takes "enable" as a clock because the register refresh it's output when enables goes high. I think Quartus inferred a latch.