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mohamis's avatar
mohamis
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3 years ago
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Why do I get the following relsult in my FIR filter output

Hello, I want to simulate my FIR filter in Verilog. But I get the wrong result. For example, when simulating a complete sinusoidal wave as input, I get the following result:   Here is...
  • FvM's avatar
    FvM
    3 years ago
    You are using logical right shift for signed variables which corrupts the sign bit. Try arithmetic shift.
mohamis's avatar
mohamis
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3 years ago

Thank you! excellent answer. After doing some minor changes to my design (especially those which you've mentioned), my ideal simulation in modelsim worked great. However, after synthesizing my project using design vision, I could not get appropriate results (I mean in non-ideal simulation using the files which were produced by design vision). it gives a lot of &hold and &setup time error and output is completely don't care. I have checked the schematic view in synthesizer. It seems flawless. just in the log file, synthesizer said:

Warning: Verilog writer has added 4 nets to module FIR filter using SYNOPSYS_UNCONNECTED_ as prefix. Please use the change_names command to make the correct changes before invoking the Verilog writer. (VO-11)

Can you help me?

Thank you

mohamis's avatar
mohamis
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3 years ago

UPDATE

When I click on check design in synopsis, the following warnnings come up:

Warning: In design 'FIR_Filter_DW01_add_0', port 'CI' is not connected to any nets. (LINT-28)
Warning: In design 'FIR_Filter_DW01_add_0', port 'CO' is not connected to any nets. (LINT-28)
Warning: In design 'FIR_Filter_DW01_add_1', port 'CI' is not connected to any nets. (LINT-28)
Warning: In design 'FIR_Filter_DW01_add_1', port 'CO' is not connected to any nets. (LINT-28)
Warning: In design 'FIR_Filter_DW01_add_2', port 'CI' is not connected to any nets. (LINT-28)
Warning: In design 'FIR_Filter_DW01_add_2', port 'CO' is not connected to any nets. (LINT-28)
Warning: In design 'FIR_Filter', the same net is connected to more than one pin on submodule 'add_2_root_add_0_root_add_59_6'. (LINT-33)
Net 'add_6_root_add_59_6/carry[6]' is connected to pins 'A[7]', 'A[6]''.

Do these warnings cause error in modelsim?