mohamis
New Contributor
New ContributorWhy do I get the following relsult in my FIR filter output
Hello,
I want to simulate my FIR filter in Verilog. But I get the wrong result. For example, when simulating a complete sinusoidal wave as input, I get the following result:
Here is...
- You are using logical right shift for signed variables which corrupts the sign bit. Try arithmetic shift.
