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Jiayi_H_Intel's avatar
Jiayi_H_Intel
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Why device has stopped receiving configuration data when programming?

Hi, I am initializing 2 Gen4x8 R-tile Pcie HIP(one is upstream/upstream, the other is downstream/downstream). Compilation using Quartus 21.2 passed successfully. But when I try to program the sof...
  • Jiayi_H_Intel's avatar
    Jiayi_H_Intel
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    Hi,

    Here is the device I use: AGIB027R29A1E2VR0

    And I am using these pins for ref clock:

    For EP side:

    refclk_pcie_14c_ch1_p(n) : CR70 : input : Current Mode Logic (CML) : 0V : 14C

    refclk_pcie_14c_ch1_p : CU68 : input : Current Mode Logic (CML) : 0V : 14C

    refclk_pcie_14c_ch0_p(n) : DM70 : input : Current Mode Logic (CML) : 0V : 14C

    refclk_pcie_14c_ch0_p : DR68 : input : Current Mode Logic (CML) : 0V : 14C

    For RP side:

    refclk_pcie_rp_ch0_p(n) : FV26 : input : Current Mode Logic (CML) : 0V : 15A

    refclk_pcie_rp_ch0_p : GA27 : input : Current Mode Logic (CML) : 0V : 15A

    refclk_pcie_rp_ch1_p : GY26 : input : Current Mode Logic (CML) : 0V : 15A

    refclk_pcie_rp_ch1_p(n) : HC27 : input : Current Mode Logic (CML) : 0V : 15A

    Anything incorrect with my assignment?