Why can't I generate a PCIe example design？

Hi,

Can I know which version of quartus you are using ?

Normally this error happen when

When you clean project, the folder of IP in your case XXX.ip is being deleted.

Therefore, you have to re-generate HDL of XXX.ip before you can generate HDL of your qsys system.

Then add_fileset_file "file not found" error should be resolved.

Regards,

Wincent_Intel