Honored ContributorWhen I tried to do simulation, a window popped out with the error:
"No simulation input file assignment specified on Simulator page of the Settings Dialog box". I checked the '"Assignments->Settings", I found I included my vwf file into the project. Then, why can't I do simulation?.... Your advice and help are highly appreciated!
Honored ContributorAssignments -> Settings -> Simulation and add the file there...
Honored ContributorThank for reply.
Do yo mean I should go to "Assignments->Settings->EDA Tool Settings->Simulation?Honored ContributorNo, that's for creating an output file to do simulations in a 3rd party tool. In the Assignments -> Settings box, along the left side where you see things like Files and EDA Tool Settings, there should be one called Simulator Settings, and you add the file there.
Honored ContributorThank you! It works!
Honored ContributorHonored ContributorI got the same problem,thank you
Honored ContributorYes, I got it. Thanks alot :D
Honored ContributorI want to execute D_FF like this into DE1 kit, but I do not know to use clock pin, reset for KIT. Please, help me
library ieee; use ieee.std_logic_1164.all; entity d_ff is port( clock: in std_logic; d: in std_logic; q: out std_logic ); end d_ff; architecture arch_dff of d_ff is begin process(clock) begin if (clock'event and clock='1') then q <= d; end if; end process; end arch_dff;Honored Contributor
