Occasional Contributor
Regular ContributorHello JJ,
I would like to get some clarification from you first.
What is the FPGA device that you use?
What is the difference between DC1M and DC50?
Regards,
Aqid
Super ContributorHi,
50 ohm load termination (oscilloscope setting "DC50") creates essentially a voltage divider between source and load impedance. In case of 50 ohm source termination, you get about 50% output level.
67 % output level (1.0/1.5) indicates 25 ohm output impedance, sounds plausible for higher drive strength setting. Expected 1.5 V would be achieved with zero output impedance which isn't feasible.
Occasional ContributorHi FvM,
Yes, your explanation make sense. The current drive strength i am using is 12mA, which is at the high end of the setting.
Hi Aqid,
I am using Stratix V : 5SGXMA3K3F40C4.
DC1M = 1Mohm load and DC50 = 50 ohm.
Where in stratix V spec that state down that with output pin termination set to off, the impedance of the output port is depend on the current strength setting and is there a table in the spec listing down what is the impedance/termination for the output port relative to the current strength (2mA to 12mA) for 1.5V IO standard and other standard?
Occasional ContributorHi Aqid,
Appreciated if you can help me out on the question i have above.
Regards, JJ
