Honored Contributor
Honored Contributorshort answer - dont use while loops for synthesisable VHDL. You have tried to write VHDL as if it is C. VHDL is NOT a programming language. I suggest you delete all your VHDL, draw out your circuit and only re-write the VHDL when you fully understand the circuit first.
long answer - loops are unrolled to produce parrallel hardware. So you always have to assume the worst case, which here means that (im going to assume that synchro_gear is not constrained) the worst case is synchro_gear is 2^31. This means it will take a lot of loops to exit, and it is trying to place over 10,000 adders and subtractors. This is very poor design. The way to fix it is as I said above for the short version.
