Honored Contributor
Honored ContributorI'm afraid my suspicion was about right - your code doesn't really lend itself to FPGA gates...:oops:
You have 18 (yes - eighteen!) multipliers instantiated in your statement. Furthermore, you're asking your FPGA to evaluate this statement in a single clock cycle. Finally, you say you're intending to have a statement like this for every letter of the alphabet... So, I'm not surprised you've run out of FPGA resource. You need to reconsider how your code is written having first (I suggest) done a little more background reading. Whilst FPGAs can create multipliers it really can't implement them as you've written. To do what you're trying to do you need to learn about pipe-lining your code. This means splitting your code up to evaluate your statement over multiple clock cycles. Do little pieces at a time. Given what you're trying to do you will have plenty of clock cycles in which to do this. I've not had a good look through this link but the opening paragraph tells me it's on the right lines - what is pipelining? explanation with a simple example in vhdl (http://vhdlguru.blogspot.co.uk/2011/01/what-is-pipelining-explanation-with.html). Start inserting some (lots) of flip flops in your code. Cheers, Alex
