what's non-inverted input pin ?

Hello,

During complete my project, I stuck at a problem with pll.

I use kit Cyclone III devlopment kit

I try to use clock 50MHz to feed pll1 by pin AH15. During synthesing and analyzing it returns error:

Error (15065): Clock input port inclk[0] of PLL "adc_pre:inst1|CLOCK_GEN:clkinst|altpll:altpll_component|CLOCK_GEN_altpll:auto_generated|pll1" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block

Info (15024): Input port INCLK[0] of node "adc_pre:inst1|CLOCK_GEN:clkinst|altpll:altpll_component|CLOCK_GEN_altpll:auto_generated|pll1" is not connected

Also, I found a solution here. but it doesn't help me. I try to write the code to the .qsf file in folder of quartus project. But it doesn't help.

http://www.altera.com/support/kdb/solutions/rd02012010_744.html

What does the " non-inverted input pin" mean?

and How can I resolve this problem?

Please help me, thanks