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Altera_Forum
Honored Contributor
Honored Contributorwhat's non-inverted input pin ?
Hello, During complete my project, I stuck at a problem with pll. I use kit Cyclone III devlopment kit I try to use clock 50MHz to feed pll1 by pin AH15. During synthesing and analyzing it re...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Have you see the link I posted: "http://www.altera.com/support/kdb/solutions/rd02012010_744.html". This link tells about this error but I don't understand so much. --- Quote End --- The link is about a problem related to formal verification rather than regular design implementation. As Dave told, the clock pin can be used as single ended clock input without restrictions. Either you have made additional settings not mentioned in your post, or you are facing a specfic Quartus bug.
