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I connect it to pin AH15, which is oscilator 50Mhz, so is that DIFCLKIN_N or any kind of inverted signal?
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I cannot tell you without knowing the exact part number of the FPGA. Post a link to the "Cyclone III development kit" you are using and I'll look.
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And why does and how can Quartus seperate two kind of clocks when they are only about 180 o different phase.
Sorry if the questions just like stupid, I don't study any course of FPGA, I study by myself. Thanks,
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I'm not sure what you are asking here. If the signal is defined as differential, then the FPGA will use a differential receiver to receive the clock. If however the clock is defined as single-ended, then the FPGA will use a single-ended buffer. In that case, the single-ended signal may be restricted to enter the device on the DIFFCLKIN_P pin. I don't recall whether this is always the case. Typically I synthesize a design using Quartus to confirm clock assignments. The details on which clock pins route to what PLLs can also be found in the handbook for the device you are using.
Start by posting a link to the kit, and I'll point you to the appropriate place in the Cyclone III handbook where it provides the information.
Cheers,
Dave
Honored Contributor
