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Honored Contributor
Honored Contributorwhat's non-inverted input pin ?
Hello, During complete my project, I stuck at a problem with pll. I use kit Cyclone III devlopment kit I try to use clock 50MHz to feed pll1 by pin AH15. During synthesing and analyzing it re...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- It means that the PLL needs to be driven from a pin with a CLKIN or DIFFCLKIN_P function, but not a DIFFCLKIN_N (inverted input) function (unless your clock is a differential input, in which case, both DIFFCLKIN_P and N would be used). Cheers, Dave --- Quote End --- Hi Dave, I connecti it to pin AH15, which is oscilator 50Mhz, so is that DIFCLKIN_N or any kind of inverted signal? And why does and how can Quartus seperate two kind of clocks when they are only about 180 o different phase. Sorry if the questions just like stupid, I don't study any course of FPGA, I study by myself. Thanks,
