What's LVDS Setup and Hold time?

Setup and hold times are properties of receivers (inputs), not transmitters (outputs).

Which means, the setup and hold times you read in the ADC's datasheet don't apply to the ADC's output signals.

What is important are receiver's setup and hold times.

Setup time (tSU) is the time the data signal at the receiver's input needs to be stable before the clock edge.

Hold time (tH) is the time the data signal at the receiver's input needs to be stable after the clock edge.

This is much easier to understand if you draw the clock and data signals for your system.

You need to take into account the ADC's output timings (tCO, center or edge aligned) and the board delays for both clock and data signals.

However, you won't be able to find the FPGA's tSU and tH values anywhere. :)

Instead, you have to tell the FPGA's software about the input signals' timing. Then the software will adjust the FPGA's programmable input delays to meet your input signals' timing.

Please read the TimeQuest cookbook for this.

But basically, what you need to do is go back to that timing diagram above and figure out this: at the FPGA's input, what's the delay between the clock edge and the signal change? And you need to figure a max and min case for this.