What is Timing between nCEO and DCLK in a multi-device AS Configuration ?

Not sure I can add much here, as we're doing a single Cyc III device design, and we're using AS Mode. But we see similar timing issues (or lack thereof) in that we come out of Reset phase with nCONFIG and nSTATUS having gone High, but we never see nCS/nCSO transition to select the EPCS and we never see DCLK out of the FPGA. So, we're slogging around with that problem....looking at whether the voltages on the MSEL lines are appropriate, and whether we're putting the Cyc III into the mode that we think it's in.

The point I wanted to make is that the more recent version of Cyc III documentation (2012) doesn't contain some of the signaling protocol information that we found on an earlier version of a document (2008); I thought I'd share that link, just in case it didn't turn up in any of your web searching.

http://cp3.irmp.ucl.ac.be/upload/wg_hardware/epcsx

This version of a document on EPCS devices has opcodes and signal timing specific to communication between FPGA and EPCS devices that we didn't see in mose recent documentation.

Hope this helps.

cheers,

jim