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Clarifications:
The 3rd Board was previously not available to test this FPGA configuration issue with because of a bad power regulator.
The regulator was fixed and I am able to power the board and attempt to program the FPGA's on it. If it did not have
the problems the other boards had I would have replaced the FPGA's on the first two boards.
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Ok, I see.
Its still not clear from this brief discussion what works and what does not. If you can program the FPGAs via JTAG, then that would indicate the issue is related to EPCS configuration.
If some boards work and others do not, then it implies either a timing or waveform (signal integrity) issue.
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I am about to concede to trying to configure the FPGA's from something other than the EPCS with pof's. I have an alternate
set of DATA0, DCLK, nCE, etc. signals routed from another (well behaved) FPGA on the board. So I concatenate my two *.rbf's
and clock these bytes in serially. So do you have a reference for the details of doing this ? Is the serial stream MSB first ?
Do I need to do any byte swapping things?
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The Handbook for the device has pretty good details on what is required. PS data is serialized LSB-to-MSB. This doc has some notes:
http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf Cheers,
Dave
Honored Contributor
