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Note however that "Table 1–2. Maximum Allowed Overshoot During Transitions over a 10-Year Time Frame for Cyclone IV Devices" on p449 implies that the I/O pins are actually 4.2V tolerant (100% duty cycle), so if you did drive the pin with 2.5V, it should not cause damage.
Personally, I prefer to be conservative and would stay within the logic level limits imposed in Table 1–15. Texas Instruments and Fairchild have lots of dual-supply buffers that make it easy to interface 2.5V or 3.3V signals into a 1.8V FPGA bank.
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Instead of maximum ratings and allowed overshoot, we would primary refer to Table 1–3.
recommended operating conditions for cyclone iv e devices , which specifies 3.6 V maximum input voltage independent of VCCIO.
It should be also noted that previous FPGA families, e.g. Cyclone II had been advertised with a MultiVolt-I/O feature, allowing e.g. to feed 3.3V input level to a 1.5V bank. It's not completely clear what motivates the Vih,max specifications in table 1-15.
Interestingly, the Cyclone V datasheet releases Vih,max for the 2.5V IO-standard to 3.6V again. Does this involve a hardware change? I guess it's just arbitrary.
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