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Altera_Forum
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12 years ago

What is the suitable Voltage level for clock input? Vccio , Vccd_pll ?

I'm designing board with cyclone IV, so i was checking several reference designs, and I looked in the Cyclone III LS FPGA, in this design the designer set the bank 7 and bank 8 with a Vccio=1.8 (the ...