Honored Contributor
Honored ContributorSince the clock, switch, and push-buttons are all inputs to the 1.8V powered bank, what you need to confirm is that this will not damage the I/O cell.
The logic levels will still be interpreted correctly, since 0V will be a low, and anything above 1.8V will be a high. So lets look at the Cyclone IV Handbook: http://www.altera.com/literature/lit-cyclone-iv.jsp Look at "I/O Standards" on p117, "Table 6–3. Cyclone IV Devices Supported I/O Standards and Constraints". Look at "I/O Standard Specifications" on p458, "Table 1–15. Single-Ended I/O Standard Specifications for Cyclone IV Devices" This table indicates that Vin(max) = 2.25, when VCCIO = 1.8V. Based on this, I would not drive a 2.5V signal onto a 1.8V bank. Note however that "Table 1–2. Maximum Allowed Overshoot During Transitions over a 10-Year Time Frame for Cyclone IV Devices" on p449 implies that the I/O pins are actually 4.2V tolerant (100% duty cycle), so if you did drive the pin with 2.5V, it should not cause damage. Personally, I prefer to be conservative and would stay within the logic level limits imposed in Table 1–15. Texas Instruments and Fairchild have lots of dual-supply buffers that make it easy to interface 2.5V or 3.3V signals into a 1.8V FPGA bank. Cheers, Dave
